Field of the Invention
The present invention relates to a measurement circuit and method for measuring a clock node to output node delay of a flip-flop.
Description of the Prior Art
There are many situations where it is desirable to measure the clock node to output node delay of a flip-flop. For example, such flip-flops will often be used extensively in data processing systems, and when designing such data processing systems it is useful to know the clock to output node delay of the flip-flop, along with information about the delay associated with other circuit components. However, the known techniques for measuring the clock to output node delay (hereafter referred to as the C-Q delay) are typically quite complex, and often require the use of sophisticated analog circuits, such as TDC (Time to Digital Converter) circuits, in order to measure the C-Q delay.
Some known techniques for measuring the C-Q delay are illustrated by the following two papers:
[1] Nikola Nedovic et al, “A Test Circuit for Measurement of Clocked Storage Element Characteristics,” IEEE J. Solid-State Circuits, vol. 39, no. 8, pp, 1294-1304, August 2004. This paper use many delay lines and extra logic gates (MUXs). The delay lines have capacitors to adjust the delay, and they require custom-layouts (hence increased design-time). Further, there is no way to compensate mismatch errors that occur due to the extra logic gates.[2] Chen Kong Teh et al, “A 77% Energy-Saving 22-Transistor Single-Phase-Clock ing D-Flip-Flop with Adaptive-Coupling Configuration in 40 nm CMOS,” IEEE Int. Solid-State Circuits Conf. (ISSCC) 2011 Dig. Tech. Papers, pp. 338-339, 2011, This paper adds many extra logic gates (XOR, MUXs) to a device under test to measure C-Q delays, but does not provide any mechanism for compensating for any mismatches that they introduce.
Accordingly, it will be appreciated that the known techniques are often complex, requiring many additional components, and often custom layouts, and further suffer from inaccuracies due to mismatch errors that can be introduced. Accordingly, it would be desirable to provide an improved technique for measuring the C-Q delay of a flip-flop.